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mirseo/JSilicon

GitHub SystemVerilog Apache License 2.0

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

★ 101 Forks 10 mirseo Updated 06 Jun 2026

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